Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - fpga programming and simulation

Search list

[Other resource] shzzh

Description: 这是在FPGA上实现的数字钟功能，用VERILOG语言编程，已功过编译，仿真验证-This is the FPGA to achieve the digital clock function with verilog programming language, compiler has merits and demerits. Simulation
Platform: | Size: 64149 | Author: 吴乔红 | Hits:

[VHDL-FPGA-Verilog] FPGAdigitaltimer

Description: 本设计要实现一个具有预置数的数字钟的设计,具体要求如下: 1. 正确显示年、月、日 2. 正确显示时、分、秒 3. 具有校时,整点报时和秒表功能 4. 进行系统模拟仿真和下载编程实验,验证系统的正确性 -designed to achieve this with a number of preset clock design, and specific requirements are as follows : 1. Display correctly, , 2. display correctly when, minutes and 3 seconds. with school, the whole point timekeeping and stopwatch functions 4. for system simulation and download programming an experiment to test the correctness of system
Platform: | Size: 502784 | Author: wangpeng | Hits:

[VHDL-FPGA-Verilog] shzzh

Description: 这是在FPGA上实现的数字钟功能，用VERILOG语言编程，已功过编译，仿真验证-This is the FPGA to achieve the digital clock function with verilog programming language, compiler has merits and demerits. Simulation
Platform: | Size: 63488 | Author: 吴乔红 | Hits:

[SCM] 9

Description: 本文介绍了两种分频系数为整数或半整数的可控分频器的设计方法。其中之一可以实现50％的奇数分频。利用VHDL语言编程，并用QUARTERS||4.0进行仿真，用 FPGA 芯片实现。 关键词：半整数，可控分频器，VHDL, FPGA -This article describes two kinds of sub-frequency coefficient is an integer or half-integer divider controllable design method. One of them can achieve 50 of the odd-numbered sub-frequency. The use of VHDL language programming, and QUARTERS | | 4.0 simulation, using FPGA chip. Key words: semi-integer, controllable divider, VHDL, FPGA
Platform: | Size: 180224 | Author: 陈金豹 | Hits:

[SCM] digital_cymometer

Description: 简易数字频率计利用复杂可编程逻辑器件FPGA,VHDL编程将所有功能模块集成在一块芯片上。功能模块包括时基脉冲发生器、计数器、数据锁存器和显示电路4部分。设计时先分别设计各功能模块，并调试得到正确仿真结果，然后将各个功能模块组合起来。最后作整体仿真、下载，得到实物。由于采用纯数字硬件设计制作，稳定性、可靠性远远高于使用单片机或模拟方式实现的系统，外围电路简单。该数字频率计达到预期要求，实现了可变量程测量，测量范围0.1Hz—9999MHz，精度可达0.1Hz。-Simple digital frequency meter using complex programmable logic device FPGA, VHDL programming integration of all functional modules on a single chip. Functional modules, including time-base pulse generator, counters, and display data latch circuit 4. Design before the design of various functional modules, respectively, and debugging simulation results correctly, and then combine the various functional modules. Finally, for the overall simulation, download, be kind. As a result of the production of digital hardware design, stability, reliability is far higher than the use of single-chip microcomputer or analog means of the system, a simple peripheral circuits. The digital frequency meter to achieve the desired requirements of the variable-range measurement, measuring range 0.1Hz-9999MHz, accuracy up to 0.1Hz.
Platform: | Size: 412672 | Author: 严术骞 | Hits:

[Communication] serialcomuniactionsource_files

Description: 用于FPGA与232通信的编程设计，用VERILOG语言编写的，在ISE中仿真-232 communications for FPGA programming and design, using the VERILOG language in ISE Simulation
Platform: | Size: 7168 | Author: mengzi | Hits:

[Program doc] szjdyccs

Description: 针对数字信号通过基带系统远程传输问题, 分析了对信号进行编码和频谱变换的原理。在系统结构设计的基础上, 重点介绍了采用FPGA 编程实现基带信号编码、频谱变换、位定时提取的过程, 给出了关键环节的仿真波形。利用伪码对实际系统进行了测试, 证明能可靠地完成基带信号的传输。-For digital signal through the base-band system long-distance transmission problem, analysis of the signal coding and spectrum transform principle. In the system based on the structural design, focusing on the use of FPGA programming baseband signal coding, spectrum transform, bit timing extraction process, and gives a key link in the simulation waveforms. Using pseudo-code of the actual system has been tested, proven to be reliable and complete base-band signal transmission.
Platform: | Size: 216064 | Author: x | Hits:

[VHDL-FPGA-Verilog] fsh

Description: 这是我的毕业可用8位的LED显示，有小数点的。设计哦，可以用的。可供参考-VHDL-based digital frequency meter With the rapid development of electronic technology, FPGA/CPLD appear in its high-speed, high reliability, series parallel mode of outstanding merit widely used in the electronic design, and EDA design represents the future direction. In this paper, based on the principle of equal precision frequency meter measuring frequency is a typical application. Through the FPGA using VHDL hardware description programming language, in addition to the plastic part of the measured signal, key input part and the digital display part, the rest all in one FPGA chip implementation, such as 8-bit digital precision frequency meter. Using Quartusll integrated development environment for editing, synthesis, wave simulation, and download to the FPGA, by the actual circuit testing. And other precision frequency meter has high availability and reliability, high precision, and accuracy varies with frequency. System frequency measurement range of up to 0-25MHz, the frequency m
Platform: | Size: 4354048 | Author: 战魔 | Hits:

[VHDL-FPGA-Verilog] FPGA

Description: 本文采用FPGA来模拟实际的乒乓球游戏。本设计是基于Altera 公司的FPGA Cyclone II 芯片EP2C35 的基础上实现，运用Verilog HDL 语言编程，Quartus II 软件上进行编译、仿真，最终在Altera 公司的DE2 开发板上成功实现下载和调试-In this paper, FPGA to simulate the actual tennis game. The design is based on Altera' s FPGA Cyclone II EP2C35 on the basis of the chip, using Verilog HDL language programming, Quartus II software to compile, simulation, and ultimately in the Altera DE2 development board and the company successfully download and debug
Platform: | Size: 183296 | Author: 李丽 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: LED控制,实现LED功能！源代码！8.2 .3程序设计与仿真 例1：FPGA驱动LED静态显示 --文件名：decoder.vhd --功能：译码输出模块，LED为共阳接法 -LED controls, LED function to achieve! Source code! .3 8.2 programming and simulation case 1: FPGA driving LED static display- File Name: decoder.vhd- Function: decode output module, LED common anode connection for the
Platform: | Size: 1024 | Author: pepsiprite | Hits:

[VHDL-FPGA-Verilog] sixiangzaibosheji

Description: 本代码采用Altera公司的FPGA为主控芯片，以开发软件QuartusⅡ为工具。采用EDA设计中的自顶向下与层次式设计方法使用精简的DDS算法完成了输入为14MHz，输出四路频率为70MHz的四相序正弦载波（相位分别为0°、90°、180°、270°）的设计。利用Verilog HDL语言进行了程序设计并用QuartusⅡ对设计进行了仿真，验证了其正确性。-DDS algorithm with simplified input for the completion of 14MHz, 70MHz output frequency of the four four-phase sequence of a sinusoidal carrier (phase were 0 °, 90 °, 180 °, 270 °) design. Using Verilog HDL language for the programming and design with the Quartus Ⅱ of the simulation to verify its correctness.
Platform: | Size: 5120 | Author: biyuming | Hits:

[DSP program] DSP_FPGAcontrol232

Description: 传统的DSP 控制通常针对的是三相系统,其外设资源不能满足多相逆变器的控制要求,文中 提出一种DSP + FPGA 的控制器解决方案. 特别利用了FPGA 逻辑资源丰富,编程灵活的特点,设 计了译码电路、脉冲发生、串口通信、看门狗保护、硬件状态锁存等功能单元,在有效扩展系统功能 的同时,降低了运算单元的负荷,提高了整体性能. 对设计进行了时序仿真,并将其应用于8 MW逆变器的控制系统中,结果验证了设计方案的功能性与可靠性.-Traditional DSP control is usually targeted at three-phase system, its peripherals resources can not meet the requirements of multi-phase inverter control, the paper presents a DSP+ FPGA controller solutions, especially the use of the FPGA logic resource-rich, flexible programming characteristics, the design of the decoding circuit, pulse, serial communication, watchdog protection, hardware, latches and other functional unit state, the effective expansion of system functions, while reducing the computing unit load, improve the overall performance of the design for timing simulation, and applied to 8 MW inverter control system, the results validate the design' s functionality and reliability.
Platform: | Size: 581632 | Author: ywj | Hits:

[VHDL-FPGA-Verilog] plj

Description: 本设计采用基于FPGA等精度频率设计原理和MCU8051软核做微处理器。采用VHDL语言，成功的编写出了设计程序，并在Qutus II软件环境中，对编写的VHDL程序进行了仿真，得到了很好的效果。最，给出了较详细的设计方法和完整的程序设计以及调试结果。-This design uses FPGA-based design principles and other precision frequency MCU8051 do soft-core microprocessor. Using VHDL language, the successful preparation of a design process, and Qutus II software environment, the procedures for the preparation of the VHDL simulation, to get good results. Most, gives a more detailed design and full programming and debugging the result.
Platform: | Size: 561152 | Author: zhao | Hits:

[VHDL-FPGA-Verilog] 11111

Description: 1、用FPGA/CPLD实现HS162字符液晶显示。 2、分析相应的功能要求，分析CPLD与字符液晶HS162的接口典型电路。 3、利用状态机的设计方法，通过指令编程实现对HS162-4液晶模块的读/写操作，以及屏幕和光标的操作。 4、编写模块的Verilog HDL语言的设计程序。 5、在Quartus II软件或其他EDA软件上完成设计和仿真。 -This design of a CPLD-based controls HS162 to achieve character LCD display. The use of state machine design, programming by instruction of HS162 LCD module s read/write operations, as well as screen and cursor operations. Verilog HDL module written language design process. I used Quartus II software to complete the design and simulation. Primarily through software programming of CPLD, and provide power, clock, download the program, and reset other peripheral circuits necessary to achieve control of the character LCD to display the default character.
Platform: | Size: 1046528 | Author: kevin mk li | Hits:

[VHDL-FPGA-Verilog] VHDL-programming-and-simulation

Description: EDA中FPGA 设计的四种常用思想与技巧实例　-The FPGA design four common ideas and skills
Platform: | Size: 5808128 | Author: xiaoyu | Hits:

[VHDL-FPGA-Verilog] drom

Description: FPGA rom硬件语言文件 用于输出正弦序列数字信号--- megafunction wizard: ROM: 1-PORT -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: altsyncram -- ============================================================ -- File Name: drom.vhd -- Megafunction Name(s): -- altsyncram -- -- Simulation Library Files(s): -- altera_mf -- ============================================================ --************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 8.0 Build 215 05/29/2008 SJ Full Version --************************************************************ --Copyright (C) 1991-2008 Altera Corporation --Your use of Altera Corporation s design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditi
Platform: | Size: 2048 | Author: 李小狼 | Hits:

[Other] FPGA-courseware

Description: 此课件从FPGA的概念入手开始讲，第一章讲FPGA的概念和设计流程以及设计工具，第二章讲XILINX FPGA器件和产品，第四章讲仿真，第五章讲使用XST综合设计和基于QUARTUS的编译与器件编程，第六章讲各种配置，第七章为编程风格和时钟，第八章最多，共24节讲了利用FPGA实现所有单片机的功能和典型的系统设计-This courseware starting from the FPGA concept began to speak, the first chapter stresses the concept of FPGA design tools and design processes as well as the second chapter stresses XILINX FPGA devices and products, the fourth chapter speaks simulation, chapter stresses based on the design and use XST synthesis QUARTUS compilation and device programming, speaking a variety of configurations Chapter VI, VII and the clock for the programming style, VIII maximum of 24 talked about the use of single-chip FPGA implementation of all the functions and typical system design
Platform: | Size: 9306112 | Author: John | Hits:

[VHDL-FPGA-Verilog] EP2C8-2010_FPGA

Description: EP2C208C8 FPGA开发源代码（芯蓝C8板） turn_on_led 点亮LED sw_led 拨动开关控制LED rider_led 跑马灯 water_led 流水灯 key_led_without_debounce 轻触开关控制LED，无按键去抖 key_led_with_debounce 轻触开关控制LED，有按键去抖 seg7x8_dynamic_disp 七段数码管动态显示 matrixKeyboard_seg7 测试矩阵键盘，七段数码管显示 beep_test 滴滴声，测试蜂鸣器 beep_matrixKeyboard 简易不同频率发声器 lcd1602_test 测试LCD1602显示 lcd1602_clock 简易时钟，LCD1602显示 vga_color_slip VGA显示彩条 vga_char VGA显示字符 uart_tx_test 串口发送测试 uart_rx_test 串口接收测试 ps2_keyboard_test PS2键盘测试，LCD1602显示-# Copyright (C) 1991-2009 Altera Corporation # Your use of Altera Corporation s design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Altera Program License # Subscription Agreement, Altera MegaCore Function License # Agreement, or other applicable license agreement, including, # without limitation, that your use is for the sole purpose of # programming logic devices manufactured by Altera and sold by # Altera or its authorized distributors. Please refer to the # applicable agreement for further details. --------------------------------------------------------------------------# # # Quartus II # Version 9.0 Build 132 02/25/2009 SJ Full Version # Date created = 09:05:11 March 14, 2010 # #--------------
Platform: | Size: 3846144 | Author: wqc | Hits:

[Software Engineering] 11

Description: 介绍了应用FPGA芯片和硬件描述语言(VHDL)设计微波炉控制器系统的方法。系统使用VHDL编程实现各底层模块的功能，顶层的设计采用图形输入完成。论文主要阐述模块化设计的思想和状态图的描述方法，以及他们在硬件描述语言中的应用，并展示了其在Quartus II 开发系统下的仿真结果。-This paper introduces the application of FPGA chip and the hardware description language (VHDL) method for controller system design of microwave oven. The system uses the VHDL programming functions of the underlying module, the design by the graphic input complete. This thesis mainly discusses the idea of modular design and state diagram describing method, and their application of hardware description language, and show it in the Quartus II development system under the simulation results.
Platform: | Size: 1458176 | Author: 十禅 | Hits:

[assembly language] FPGA-Traffic-Light-Controller

Description: （1） 学习和掌握了解分频电路、通用同步计数器、异步计数器的使用方法； （2） 理解Moore和Mealy两种状态机的一般编程方法，能够按工程控制需求设计相应的逻辑和时序控制程序。 以开发板上的六盏LED小灯模拟，三盏小灯模拟一个方向的红黄绿交通灯灯，用VHDL语言编程实现红绿交通灯控制程序。 -(1) to learn and master the understanding of frequency division circuit, universal synchronous counter, asynchronous counter to use (2) to understand Moore and Mealy two state machine of the general programming method, according to engineering control requirements to design the corresponding logic and timing control procedures. To the development of the six small LED lights on the board simulation, three small lights to simulate a direction of the red, yellow and green traffic lights, using VHDL language programming to achieve red and green traffic light control program.
Platform: | Size: 64512 | Author: Cherry_RF | Hits:
« 12 »

CodeBus www.codebus.net